1. Field of the Invention
The present invention relates to a semiconductor memory device. The semiconductor memory device according to the present invention is applicable to a storage capacitance type dynamic random access memory (dynamic RAM) in which information is stored in a storage capacitor.
2. Description of the Related Arts
A memory call of a storage capacitance type dynamic RAM, is constituted by a storage capacitor for storing information and a transfer transistor for reading and writing information. The gate of the transfer transistor is connected to a word line, the source of the transfer transistor is connected to a bit line, and the drain of the transfer transistor is connected to the storage electrode of the storage capacitor.
In a memory cell array of the storage capacitance type dynamic RAM, a plurality of bit lines is arranged in a longitudinal direction and a plurality of word lines is arranged in a lateral direction. The two adjacent bit lines connected to the same sense amplifier at one end of each the two bit lines constitute a folded bit line type arrangement.
A transfer transistor is connected to a bit line through a bit line contact point, also known as a bit line contact area. In the spaces defined by a sequence of bit lines and a sequence of word lines, the drain of a transfer transistor is connected to a storage capacitor electrode through a storage capacitor contact area. Between two adjacent word lines, the bit line contact areas are arranged for every other bit line. Between two adjacent word lines, the storage capacitor contact areas are arranged in sequence.
Two adjacent memory cells constitute a memory cell pair which has a single common bit line contact area. One side transfer transistor is connected between one side storage capacitor contact area and the bit line contact area, and the other side transfer transistor is connected between the other side storage capacitor contact area and the bit line contact area.
In a prior art arrangement of an array of memory cells of a storage capacitance type dynamic RAM, the storage capacitor contact areas are arranged closely in sequence in a lateral direction, but the bit line contact areas are arranged only for every other bit line in longitudinal direction. Accordingly, the portion where the bit line contact area does not exist constitutes an unused wasteful space. This is not advantageous for realizing a highly integrated storage capacitance type dynamic RAM.